integrated circuit systems, inc. general description features ics91309i preliminary product preview 0770a?04/30/03 block diagram high performance communication buffer pin configuration zero input - output delay frequency range 10 - 133 mhz (3.3v) 5v tolerant input ref high loop filter bandwidth ideal for spread spectrum applications. less than 125 ps cycle to cycle jitter skew controlled outputs available in 16 pin, 150 mil ssop, soic & 4.40mm tssop packages skew: group-to-group: <215 ps skew within group: <100 ps industrial temperature range: -40c to +85c the ics91309i is a high performance, low skew, low jitter zero delay buffer. it uses a phase lock loop (pll) technology to align, in both phase and frequency, the ref input with the clkout signal. it is designed to distribute high speed clocks in communication systems operating at speeds from 10 to 133 mhz. the ics91309i provides synchronization between the input and output. the synchronization is established via clkout feed back to the input of the pll. since the skew between the input and output is less than +/- 350 ps, the part acts as a zero delay buffer. ics91309i has two banks of four outputs controlled by two address lines. depending on the selected address line, bank b or both banks can be put in a tri-state mode. in this mode, the pll is still running and only the output buffers are put in a high impedance mode. the test mode shuts off the pll and connects the input directly to the output buffers (see table below for functionality). ics91309i comes in a 16-pin 150 mil soic, ssop or 4.40mm tssop package. in the absence of ref input, the device will enter a powerdown mode. in this mode, the pll is turned off and the output buffers are pulled low. power down mode provides the lowest power consumption for a standby condition. 16 pin ssop, soic & tssop ref clka1 clka2 vdd gnd clkb1 clkb2 fs2 clkout clka4 clka3 vdd gnd clkb4 clkb3 fs1 ics913 09i 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 functionality fs2 fs1 clka(1:4) clkb(1:4) clkout ouput source pll shutdown 0 0 tristate tristate driven pll n 0 1 driven tristate driven pll n 10 pll bypass mode pll bypass mode pll bypass mode ref y 1 1 driven driven driven pll n product preview documents contain information on new products in the sampling or preproduction phase of development. characteristic data and o ther specifications are subject to change without notice.
2 ics91309i preliminary product preview 0770a?04/30/03 pin descriptions pin # pin name pin type description 1ref 1 in input reference frequency, 5v tolerant input 2clka1 2 out buffered clock output, bank a 3clka2 2 out buffered clock output, bank a 4 vdd pwr power supply 5gnd pwr ground 6clkb1 2 out buffered clock output, bank b 7clkb2 2 out buffered clock output, bank b 8fs2 3 in function select input, bit 2 9fs1 3 in function select input, bit 1 10 clkb3 2 out buffered clock output, bank b 11 clkb4 2 out buffered clock output, bank b 12 gnd pwr ground 13 vdd pwr power supply 14 clka3 2 out buffered clock output, bank a 15 clka4 2 out buffered clock output, bank a 16 clkout 2 out buffered clock output, internal feedback notes: 1. weak pull-down 2. weak pull-down on all outputs 3. weak pull-ups on these inputs
3 ics91309i preliminary product preview 0770a?04/30/03 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs (except ref) . . . . . . . . . . . . . . gnd ?0.5 v to v dd + 0.5 v logic input ref . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to gnd + 5.5 v ambient operating temperature . . . . . . . . . . -40c to +85c storage temperature . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input & supply t a = -40 - 85c; supply voltage v dd = 3.3 v +/-10% parameter symbol conditions min typ max units input high voltage v ih 2v input low voltage v il 0.8 v input high current i ih v in = v d d 0.1 250 ua input low current i il v in = 0 v 19 100 ua output high voltage vo h io h = -12 ma 2.4 v output low voltage vo l io l = 12 ma 0.4 v operating supply current i dd outputs unloaded; ref = 66 mhz 30 45 ma powerdown current i d d ref = 0 mhz 0.3 50 ua input frequency f i 10 133 mhz input capacitance 1 c in 5pf notes: 1. guaranteed by design and characterization, not 100% tested in production.
4 ics91309i preliminary product preview 0770a?04/30/03 electrical characteristics - outputs t a = -40 - 85c; v dd = 3.3 v +/-10%; c l = 30 pf (unless otherwise specified) parameter symbol conditions min typ max units output high voltage v oh i oh = -12 ma 2.4 v output low voltage v ol i ol = 12 ma 0.4 v rise time 1 t r measure between 0.8 v and 2.0 v 1.2 2 ns fall time 1 t f measure between 2.0 v and 0.8 v 1.2 2 ns pll lock time 1 t lock stable v d d , valid clock on ref 1 ms f 1 c l = 30 pf 10 100 mhz f 1 c l = 10 pf 10 133 mhz dt1 measured at 1.4 v, fout = 66.7 mhz 40 50 60 % dt2 measured at v d d /2, fout < 50.0 mhz 45 50 55 % jitter, cycle-to-cycle 1 t j c y c-c y c measured at 66.7 mhz, loaded outputs 125 ps jitter, absolute 1 tjabs 10,000 cycles, c l = 30 pf -100 70 100 ps jitter, 1-sigma 1 tj1s 10,000 cycles, c l = 30 pf 14 30 ps skew, group-to-group 1 tsk measured at 1.4 v 215 ps skew, output-to-output 1 tsk measured at 1.4 v, within a group 100 ps skew, device-to-device 1 tdsk-tdsk measured at v d d /2,on clkout pins 700 ps delay, input-to-output 1 dr1 measured at 1.4 v 700 ps notes: 1. guaranteed by design and characterization, not 100% tested in production. duty cycle 1 output frequency
5 ics91309i preliminary product preview 0770a?04/30/03 output to output skew the skew between clkout and the clka/b outputs is not dynamically adjusted by the pll. since clkout is one of the inputs to the pll, zero phase difference is maintained from ref to clkout. if all outputs are equally loaded, zero phase difference will maintained from ref to all outputs. if applications requiring zero output-output skew, all the outputs must equally loaded. if the clka/b outputs are less loaded than clkout, clka/b outputs will lead it; and if the clka/b is more loaded than clkout, clka/b will lag the clkout. since the clkout and the clka/b outputs are identical, they all start at the same time, but different loads cause them to have different rise times and different times crossing the measurement thresholds. ref input and all outputs loaded equally ref input and clka/b outputs loaded equally, with clkout loaded more . ref input and clka/b outputs loaded equally, with clkout loaded less . timing diagrams with different loading configurations
6 ics91309i preliminary product preview 0770a?04/30/03 application suggestion: ics91309i is a mixed analog/digital product. the analog portion of the pll is very sensitive to any random noise generated by charging or discharging of internal or external capacitor on the power supply pins. this type of noise will cause excess jitter to the outputs of ics91309i . below is a recommended lay out to alleviate any addition noise. for additional information on ft. layout, please refer to our an07. the 0.1 uf capacitors should be connected as close as possible to power pins (4 & 13). an isolated power plane with a 2.2 uf capacitor to ground will enhance the power line stability. 33 ? 33 ? 33 ? 33 ? 10k ? 0.1f vdd gnd 33 ? 33 ? 33 ? 33 ? 33 ? 10k ? 0.1f vdd gnd 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ref clka1 clka2 vdd gnd clkb1 clkb2 fs2 clkout clka4 clka3 vdd gnd clkb4 clkb3 fs1
7 ics91309i preliminary product preview 0770a?04/30/03 min max min max a 1.35 1.75 .053 .069 a1 0.1 0.25 .0040 .010 a2 ? 1.50 ? .059 b 0.20 0.30 .008 .012 c 0.18 0.25 .007 .010 d e 5.80 6.20 .228 .244 e1 3.80 4.00 .150 .157 e 0.635 basic 0.025 basic l 0.40 1.27 .016 .050 n 0 8 0 8 zd see variations see variations symbol see variations see variations in inc hes common dimensions in millimeters common dimensions see variations see variations variations zd zd min max (ref) min max (ref) 16 4.80 5.00 0.23 .189 .197 .009 6/1/00 rev b n d mm. d (inch) jedec mo-137 doc# 10-0032 ordering information ics91309 y fi-t designation for tape and reel packaging i = industrial temperature package type f = ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y f i - t
8 ics91309i preliminary product preview 0770a?04/30/03 150 mil (narrow body) soic min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.33 0.51 .013 .020 c 0.19 0.25 .0075 .0098 d e 3.80 4.0 .1497 .1574 e h 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 l 0.40 1.27 .016 .050 n 0 8 0 8 variations min max min max 16 9.80 10.00 .3859 .3937 symbol see variations see variations in millimeters common dimensions in inches common dimensions see variations 1.27 basic 0.050 basic n d mm. d (inch) see variations ordering information ics91309 y mi-t designation for tape and reel packaging i = industrial temperature package type m = soic revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y m i - t seating plane seating plane a1 b a e .10 (.004) .10 (.004) h x 45 h x 45 l c index area index area 12 1 2 n d e h
9 ics91309i preliminary product preview 0770a?04/30/03 ordering information ics91309 y gi-t min max min max a--1.20 --.047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 d e e1 4.30 4.50 .169 .177 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 v ariations min max min max 16 4.90 5.10 .193 .201 10-0035 4.40 mm. body, 0.65 mm. pitch tssop (173 mil) (25.6 mil) symbol in millimeters in inches common dimensions common dimensions see variations see variations 6.40 basic 0.252 basic 0.65 basic 0.0256 basic see variations see variations n d mm. d (inch) reference doc.: jedec publication 95, mo-153 designation for tape and reel packaging i = industrial temperature package type g = tssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y g i - t index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c
|
